1. Field of the Invention
This invention relates to a multiple stage radio frequency (RF) power amplifier (PA) and more particularly to a low output impedance RF amplifier associated therewith.
2. Description of the Related Art
Hardware implementations of almost all wireless communication and control systems, employing almost all possible RF modulation techniques, include RF power amplifiers (PAs) as a necessary component. Examples of RF modulation techniques include, but are not limited to, GMSK, 8PSK, 16-QAM, 64-QAM, where the amplitude of the RF signal may always be constant or may take any value in a continuous or discrete range. Examples of such systems include, but are not limited to, cellular GSM, CDMA, W-CDMA voice and data terminals, Wi-Fi, Bluetooth, remote controls, RFID readers.
RF power amplifiers for wireless applications, such as cellular, must produce high gain and high output power levels. In a typical RF transmitter, the output power and gain requirements of the PA are met by employing multiple cascaded stages of amplification, where each stage may utilize one or more active devices such as silicon MOSFETs and BJTs, GaAs MESFETs, and HBTs.
FIG. 1a shows an example of a multi-stage PA known in the art. Significant design trade-offs are encountered in the implementation of prior art multi-stage PAs. Although FIG. 1a depicts the use of NMOSFET devices as active elements, it should be apparent to those of skill in the art that other active devices, such as other types of FETs or BJTs, could be used instead. The PA shown in FIG. 1a has two gain stages, 120 and 121, followed by the matching network 122. The output node 105 is coupled to the load, symbolically presented as resistor 113, typically 50 ohm. The matching network 122 plays the role of an impedance transformation network, which converts the relatively high load impedance of 50 ohm into a lower impedance (e.g. 5 ohm) as seen by the output 103 of the final PA stage 121. The lower impedance limits the maximum voltage swing present at node 103 necessary for injecting the needed maximum output power into the load 113. The matching network exemplified in FIG. 1a consists of the inductor 110 and capacitor 112, which, together with the output stage load inductor 108, form a tuned transformation circuit. Capacitor 111 blocks the DC voltage present at the matching network output node 104 from reaching the load 113.
The PA output amplifier stage 121 consists of the active device, MOSFET 109, connected in a common-source configuration, and the load inductor 108, connected between the output node 103 and the power supply Vdd. The current through transistor 109 is controlled by the voltage difference between the gate terminal, connected to the stage input node 102, and the source terminal, connected to ground. The drain of transistor 109 is connected to the stage output node 103. The voltage signal at the drain node is substantially in phase opposition to the voltage signal on the gate node as a direct consequence of the common-source configuration of transistor 109. Inductor 108 plays two roles: it supplies the DC power to the active device 109 and it completes the resonant transformation network in conjunction with block 122. The output amplifier stage 121 receives its input on node 102 from the preamplifier stage 120 by means of the AC coupling capacitor 115.
The preamplifier stage 120 consists of the active device, MOSFET 107, connected in a common-source configuration, and the load inductor 106, connected between the output node 114 and the power supply Vdd. The current through transistor 107 is controlled by the voltage difference between the gate terminal, connected to the stage input node 101, and the source terminal, connected to ground. The drain of transistor 107 is connected to the stage output node 114. The voltage signal at the drain node is substantially in phase opposition to the voltage signal on the gate node as a direct consequence of the common-source configuration of transistor 107. Inductor 106 plays two roles: it supplies the DC power to the active device 107 and it completes the parallel resonant tank circuit in conjunction with the input capacitance presented by block 121. In the particular circuit presented in FIG. 1a, the AC coupling capacitor 115 isolates the DC potential present at node 114 from the DC potential appropriate for the bias of the control terminal of transistor 109. In other embodiments, as a result of judiciously chosen supply voltages, capacitor 115 is eliminated and nodes 114 and 102 share the same potential. The preamplifier stage 120 receives its input on node 101.
The operation of the PA presented in FIG. 1a is qualitatively illustrated by the waveforms in FIG. 1b. The preamplifier stage 120 receives on node 101 the sinusoidal voltage waveform shown in the bottom graph. As a result, the preamplifier output node 114, and similarly the input node 102 of the amplifier stage 121, will present a voltage waveform substantially in phase opposition to the waveform on node 101, exemplified in the middle graph of FIG. 1b. Likewise, the amplifier stage 121 generates a voltage waveform at its output node 103, which is substantially in phase opposition to the waveform on node 102, exemplified in the top graph of FIG. 1b. 
Since the output amplifier 121 sees a low load impedance at node 103, the maximum current flowing through the active device 109 is large. Therefore, the active device physical size is large. A dominant non-ideality for active devices is parasitic capacitance between its terminals. Owing to its large size, device 109 presents significant capacitances between node 103 and ground, between node 102 and ground, as well as between node 103 and node 102.
The active device parasitic capacitance between node 103 and ground can be considered as embedded in the resonant transformation network and does not significantly increase the difficulty of the trade-offs involved in the design of the PA.
The active device parasitic capacitance between node 102 and ground presents a substantial capacitive load to the preamplifier. This capacitance needs to be effectively resonated out by the preamplifier's output inductor 106 or else the gain of the preamplifier would collapse to an unacceptable value. The large value of the capacitive load to the preamplifier stage poses significant design constraints on the realizable gain of the preamplifier due to the limited quality factor Q of inductor 106.
Most significantly, the active device parasitic capacitance between node 103 and node 102 opens a feedback path between the output and the input of the output amplifier 121, greatly increasing the chance of circuit instability. The circuit networks located at both the output and at the input of amplifier 121 are tuned resonant circuits, likely tuned on the same RF frequency. For signal frequencies below resonance, both the input and the output circuits present inductive impedances, which, in conjunction with the parasitic capacitance between node 103 and node 102, and the active device 109, form the structure of the Hartley sinusoidal oscillator depicted in FIG. 2.
In reference to FIG. 2, the active device 201 corresponds to device 109 in FIG. 1a. Inductor 202 corresponds to the inductive impedance presented at node 102 by the combination of inductor 106 and parasitic capacitance between node 102 and ground, when operated at a frequency below resonance. Inductor 203 corresponds to the inductive impedance presented at node 103 by the combination of inductor 108, parasitic capacitance between node 103 and ground, and matching network 122, when operated at a frequency below resonance. Capacitor 204 corresponds to the parasitic capacitance between node 103 and node 102.
The presence of a Hartley oscillator structure in the output amplifier of the PA introduces significant design constraints due to the trade-offs involved in guaranteeing that the negative impedance created by the capacitive feedback in conjunction with an inductive load does not overcome the resistive loss in the input circuit. In reference to FIG. 1a, the loss in the input circuit is dominated by the quality factor of inductor 106. As a consequence of the common-source (common-emitter) configuration, the preamplifier active device 107 contributes very little to the resistive loss. In order to insure that the condition of oscillation is not met, one or more of the following design parameters have to be traded-off. One trade-off involves reducing the quality factor Q of inductor 106. That may however, severely limit the achievable gain in the preamplifier stage 120. Another parameter involves reduction of the transconductance gain, Gm, of the output amplifier active device 109. That reduction limits the achievable gain of the output amplifier 121, and increases the maximum swing of the input node 102, significantly affecting the linearity of the PA.
A further design constraint introduced by the feedback path created by the active device parasitic capacitance between node 103 and node 102 is the resistive load reflected between the input node 102 and ground at the frequency of interest. Ideally, if the feedback parasitic capacitance were absent, the impedance presented at node 102 by the active device 109 would be purely capacitive. However, the large feedback capacitance will present a fraction of the active device's transconductance at node 102, effectively adding an additional resistive load to the preamplifier stage 120. Due to the nature of the common-source (or common-emitter) configuration of stage 120, any additional resistive load will directly convert into a proportional gain degradation. Since device 109 is a large transconductance device, the gain degradation of the preamplifier can be significant.
An approach known in the art to mitigate some of the constraints listed above inserts a matching network between the preamplifier stage 120 and the output amplifier 121. Such an interstage matching network presents a low impedance towards the input of stage 121, while maintaining a large load impedance for the preamplifier stage 120. The specific case exemplified in FIG. 1a where the AC coupling capacitor 115 is present as the link between the preamplifier stage 120 and the output amplifier 121 can be designed such that the combination of inductor 106, capacitor 115, and the parasitic capacitance between node 102 and ground form an impedance transformation matching network. FIG. 3 shows in detail the structure of the interstage matching network present in FIG. 1a. The matching network input node 301 corresponds to the preamplifier output node 114. The matching network output node 302 corresponds to the final amplifier stage input node 102. Inductor 303 and capacitor 304 correspond to inductor 106 and capacitor 115, respectively. Capacitor 305 corresponds to the equivalent capacitance seen between node 102 and ground towards the input of the final amplifier stage 121. The resonant LC structure presented in FIG. 3 is easily recognized by one skilled in the art as an impedance down-converter matching network. The ratio of the output impedance, Z302, to the input impedance, Z301, is less than 1. The output impedance, Z302, is proportional to the size of capacitor 304. If capacitor 304 is much larger than capacitor 305, then the circuit in FIG. 3 does not perform any impedance transformation. If capacitor 304 has a value similar or smaller than capacitor 305, then the circuit in FIG. 3 will create an output impedance smaller than the impedance attached to its input. The drawback of this solution is the fact that the impedance down-transformation is achieved at the cost of significant reduction in voltage swing at the input of stage 121. As a consequence, gains have to be boosted in the preamplifier and/or the output amplifier of the PA, a costly proposition.
FIG. 4a shows another example of a multistage PA where both the output amplifier stage 421 and the preamplifier stage 420 are built using MOSFET devices connected in the common-source configuration. The load 419, usually 50 ohm, is connected through the DC blocking capacitor 418 to the matching network 422 comprising capacitors 417 and 415, and the inductor 416. The output amplifier stage 421 consists of complimentary MOSFET devices, the NMOS 413 and the PMOS 412, and inductor 414 connected between node 405, and node 406. The current through transistor 413 is controlled by the voltage difference between the gate terminal, connected to the stage input node 404, and the source terminal, connected to ground. The drain of transistor 413 is connected to the stage output node 406. The voltage signal at the drain node is substantially in phase opposition to the voltage signal on the gate node as a direct consequence of the common-source configuration of transistor 413. Similarly, the current through transistor 412 is controlled by the voltage difference between the gate terminal, connected to the stage input node 403, and the source terminal, connected to Vdd. The drain of transistor 412 is connected to the stage output node 405. The voltage signal at the drain node is substantially in phase opposition to the voltage signal on the gate node as a direct consequence of the common-source configuration of transistor 412. Inductor 414 plays two roles: it allows current to flow between the NMOS and the PMOS devices so that both devices share bias current, and it completes the resonant transformation network in conjunction with block 422.
The matching network 422, in conjunction with the inductor 414, forms a lumped balun structure which simultaneously achieves differential to single-ended conversion as well as impedance transformation. FIG. 4b qualitatively illustrates the voltage waveforms present at the nodes of the PA shown in FIG. 4a. The signals at nodes 405 and 406 are in phase opposition as depicted in FIG. 4b top graph. The signals at nodes 403 and 404 (FIG. 4b middle graph) are also in phase opposition and are supplied by the preamplifier stage 420. It is observable in FIG. 4b that the voltage waveforms of the homologous outputs and inputs nodes of the amplifier stage 421 are substantially in phase opposition—e.g. nodes 406 and 404.
The preamplifier stage 420 consists of complimentary MOSFET devices, NMOS 410, PMOS 409, and inductor 411 connected between nodes 404 and 403. The current through transistor 410 is controlled by the voltage difference between the gate terminal, connected to the stage input node 402, and the source terminal, connected to ground. The drain of transistor 410 is connected to the stage output node 404. The voltage signal at the drain node is substantially in phase opposition to the voltage signal on the gate node as a direct consequence of the common-source configuration of transistor 410. Similarly, the current through transistor 409 is controlled by the voltage difference between the gate terminal, connected to the stage input node 401, and the source terminal, connected to Vdd. The drain of transistor 409 is connected to the stage output node 403. The voltage signal at the drain node is substantially in phase opposition to the voltage signal on the gate node as a direct consequence of the common-source configuration of transistor 409. Inductor 411 plays two roles: it allows current to flow between the NMOS and the PMOS devices achieving current sharing between both devices, and it cancels the capacitive reactance reflected at the input of the amplifier stage 421 at the resonant frequency. Analogous to stage 421, the signals at nodes 401 and 402 are in phase opposition as depicted in FIG. 4b bottom graph, while the voltage waveforms of the homologous outputs and input nodes of the amplifier stage 420 are substantially in phase opposition—e.g. nodes 404 and 402—as shown in FIG. 4b middle and bottom graphs.
Although the PA shown in FIG. 4 consists of complementary MOS amplifier stages, each having two inputs and two outputs, its behavior and hence, its design constraints and trade-offs, are substantially similar to those described in reference to FIG. 1. This can be easily understood by one skilled in the art, by assuming the presence of virtual grounds at middle points of inductors 411 and 414. In such a case, the amplifier stages in FIG. 4 simply look like two copies, a PMOS version and an NMOS version, of the amplifier stages of FIG. 1, stacked one above the other. As a result, this amplifier has similar stability concerns as the amplifier of FIG. 1.
Transistor 413 harbors a significant parasitic capacitance between the gate node 404 and the drain node 406. The impedance presented towards the drain node 406 by the matching network 422 in conjunction with inductor 414 is substantially equivalent to one characteristic of a resonant LC tank. At the same time, the combination of the parasitic capacitance between node 404 and ground, and a portion of inductor 411 form a resonant LC tank at the gate of device 413. The tuning frequencies of the two tanks thus formed need to be substantially similar in order to achieve an acceptable PA gain. For signal frequencies below the resonant frequency, both the drain equivalent LC tank and the gate LC tank will present an inductive impedance, which, in combination with the capacitance between nodes 404 and 406 and transistor 413, form the structure of a Hartley oscillator.
Likewise, transistor 412 harbors a significant parasitic capacitance between the gate node 403 and the drain node 405. The impedance presented towards the drain node 405 by the matching network 422 in conjunction with inductor 414 is substantially equivalent to one characteristic of a resonant LC tank. At the same time, the combination of the parasitic capacitance between node 403 and Vdd, and a portion of inductor 411 form a resonant LC tank at the gate of device 412. The tuning frequencies of the two tanks thus formed need to be substantially similar in order to achieve an acceptable PA gain. For signal frequencies below the resonant frequency, both the drain equivalent LC tank and the gate LC tank will present an inductive impedance, which, in combination with the capacitance between nodes 403 and 405 and transistor 412, form the structure of a Hartley oscillator.
As explained above, the PA illustrated in FIG. 4a embeds two Hartley oscillator structures. The oscillators are strongly coupled through the various shared components. However, the phase opposition relationship between the PFET side nodes (401, 403, 405) and the NFET side nodes (402, 404, 406) is not enforced in a free-running oscillation condition. Hence, two modes of oscillations are possible: a differential-mode oscillation, where the PFET side nodes and the NFET side nodes are substantially in phase opposition, and a common-mode oscillation, where the PFET side nodes and the NFET side nodes are substantially in phase. The two modes may appear independently or simultaneously in a given PA with the structure presented in FIG. 4a, depending on whether the condition of oscillation is met in either of the two modes. Additionally, the two modes of oscillation will likely have different oscillation frequencies. Ensuring that the condition of oscillation is not met with sufficient margin for both modes of oscillation introduces significant design constraints in the development of a PA such as the one in FIG. 4a. 